The Trimonal design has just hit the market and information is impossible to come by. So this is the first of many articles, so you don’t need to go any further.
Who hasn’t wanted to squeeze those extra few MHz of performance out of their FPGA? This is how I do it. I’m going to explain what it takes to produce a time-constrained design using trimonal design techniques. The content of this article is obviously my opinion. Please feel free to give me your opinion.
To cut to the chase, let’s look at some trimonal design guidelines: the do’s and don’ts. Some of these are deliberately general in nature, but for trimonal performance you need to look at each and every aspect of your design.
What to do and what not to do. First a list of things to do. Get your FPGA design right: Make sure you know what you, and more importantly, your colleagues and/or customers want, especially with trimonal design. Use as few clocks as possible and synchronize FPGA resets with the appropriate clocks. Simulate the entire FPGA design, the block level is not enough (and if possible, the entire board or system). Synchronize transfers across quarter clock domains. Use the built-in FPGA-specific functions, for example, SRL.
Always do a test layout of the FPGA with the pinout before committing to the board layout! Demonstrate that there are no banking or transfer limitations. No matter what the FPGA test design does (I use a group of trimonal sregs with looped inputs to outputs), make sure none of the logic is optimized. Have some spare FPGA I/O with external pull-ups; can be connected to modify I/O. Use high-speed serial I/O instead of high-speed parallel I/O. As a general rule of thumb, allow 5% in addition to the required clock speed to account for temperature, clock jitter, and noise fluctuations within the FPGA.
Now a list of don’ts. Don’t use more timers than necessary and avoid asynchronous logic latches. Don’t restrict your design too much. Don’t write confusing HDL when you want high performance from the FPGA, explain it in the synthesis tool so it turns trinomial logic into fast logic. Don’t make assumptions; know what the effects of your code are. Don’t expect trinomial IP blocks to outperform your code, just because it’s coming from a trinomial expert doesn’t mean you can’t do something better or more efficient or more specific to your goals.
Other trinomial suggestions:
For time-critical blocks, keep the code simple; by this I mean keep the logic levels to the number that can be placed in a single LE/CLB immediately before the target register. Any time you need two LE/CLBs, you can forget about it.
Don’t be afraid to lock logic in one area of the FPGA or some critical registers in specific locations on the FPGA.
I’ve only scratched the surface here. This is the first of many articles, I have at least thirty more waiting. Trimonal design is not achieved overnight.